1. Field
Various exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a controller, a semiconductor memory system, and an operating method thereof.
2. Description of the Related Art
Semiconductor memory devices are generally classified into volatile memory devices, such as Dynamic Random Access Memory (DRAM) and Static RAM (SRAM), and nonvolatile memory devices, such as Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable PROM (EPROM), Electrically EPROM (EEPROM), Ferromagnetic RAM (FRAM), Phase change RAM (PRAM), Magnetoresistive RAM (MRAM), Resistive RAM (RRAM) and flash memory.
Volatile memory devices lose data stored therein when their power supplies are interrupted, whereas nonvolatile memory devices retain data stored therein even when their power supply is interrupted. In particular, flash memory devices are widely used as storage mediums in computer systems due to their high program speed, low power consumption and large data storage capacity.
In nonvolatile memory devices, including flash memory devices, the data state of each memory cell is determined based on the number of bits stored in the memory cell. A memory cell storing 1-bit data per cell is called a single-bit cell or a single-level cell (SLC). A memory cell storing multi-bit data, i.e., 2 or more bit data, per cell is called a multi-bit cell, a multi-level cell (MLC) or a multi-state cell. Multi-bit cells are advantageous for high integration. However, as the number of bits programmed in each memory cell increases, reliability decreases and read failure rates increase.
For example, when k bits are programmed in a memory cell, one of 2k threshold voltages is formed in the memory cell. Due to minute differences between the electrical characteristics of memory cells, the threshold voltages of memory cells programmed with the same data form a threshold voltage distribution. Threshold voltage distributions are therefore based upon memory cells having 2k data values, which corresponds to k-bit information.
However, the voltage window available for threshold voltage distributions is limited. Therefore, as the value k increases, the distance between the threshold voltage distributions must decrease and the adjacent threshold voltage distributions may overlap each other. As the adjacent threshold voltage distributions overlap each other, the data that is read may include multiple error bits.
FIG. 1 is a threshold voltage distribution schematically illustrating program and erase states of a 3-bit multi-level cell (3-bit MLC) nonvolatile memory device.
FIG. 2 is a threshold voltage distribution schematically illustrating program and erase states due to characteristic deterioration of a 3-bit MLC nonvolatile memory device.
In an MLC nonvolatile memory device, e.g., an MLC flash memory device in which k-bit data is programmed in a memory cell, the memory cell may have one of 2k threshold voltage distributions. For example, a 3-bit MLC has one of 8 threshold voltage distributions.
Threshold voltages of memory cells programmed with the same data form a threshold voltage distribution due to characteristic differences between memory cells. In a 3-bit MLC nonvolatile memory device, as illustrated in FIG. 1, threshold voltage distributions having first to seventh program states ‘P1’ to ‘P7’ and an erase state ‘E’ are formed. FIG. 1 shows an ideal case in which threshold voltage distributions do not overlap and have read voltage margins therebetween.
Referring to the flash memory example of FIG. 2, memory cells may experience charge loss over time from the electrons that are lost from the floating gate or tunnel oxide film. This charge loss may accelerate when the tunnel oxide film deteriorates from numerous program and erase operations. Charge loss results in a decrease in the threshold voltages of memory cells. For example, as illustrated in FIG. 2, the threshold voltage distribution may shift to the left as the result of charge loss.
Further, program disturbance, erase disturbance and/or back pattern dependency also cause increases in threshold voltages. As the characteristics of memory cells deteriorate, as described above, threshold voltage distributions of adjacent states may overlap, as illustrated in FIG. 2.
Once threshold voltage distributions overlap, read data may have a significant number of errors when a particular read voltage is applied to a selected word line. For example, when a sensed state of a memory cell according to a read voltage Vread3 (i.e. the voltage read from the memory cell) that is applied to a selected word line is on, the memory cell is determined to have a second program state ‘P2’. When a sensed state of a memory cell according to a read voltage Vread3 applied to a selected word line is off, the memory cell is determined to have a third program state ‘P3’. However, when threshold voltage distributions overlap, the memory cell, which actually has the third program state ‘P3’, may be erroneously determined to have the second program state ‘P2’. In short, when the threshold voltage distributions overlap as illustrated in FIG. 2, read data (i.e. data which is read from a memory cell) may include a significant number of errors.
What is therefore required is a scheme for precisely determining optimal read voltages for data stored in memory cells of a semiconductor memory device.